System modelling Engineer

<p style="min-height: 1.7em;"></p><p><strong><span style="color:#222222">About Us</span></strong><span style="color:#222222"> : </span><span style="color:#000000">AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.</span></p><p><strong><span style="color:#222222">Why Now</span></strong><span style="color:#222222"> : </span><span style="color:#000000">After 18 months of intensive R&amp;D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&amp;D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.</span></p><p style="min-height: 1.7em;"></p><p style="min-height: 1.7em;"></p><p style="text-align:justify;"><strong><span style="color:#222222">About the role:&nbsp;</span></strong></p><p style="text-align:justify;"><span style="color:#000000">We are looking for an expert System Modelling Engineer to drive the modelling, integration, and performance analysis of our advanced Vertical Compute / VIMx system memory architectures.</span></p><p style="text-align:justify;"><span style="color:#000000">In this role, you will be responsible for building robust SystemC models, integrating them onto the Palladium emulation platform, and benchmarking performance against an ideal SRAM baseline for cutting-edge AI applications.</span></p><p style="text-align:justify;min-height: 1.7em;"></p><p style="text-align:justify;"><strong><span style="color:#222222">Key Responsibilities:</span></strong></p><ul><li><p style="text-align:justify;"><strong><span style="color:#222222">System-Level Modeling</span></strong><span style="color:#222222">: Design, validate, and deliver robust SystemC software models for individual VIMx components and the broader memory hierarchy.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Multi-Bank Configurations</span></strong><span style="color:#222222">: Model and simulate complex multi-bank system memory configurations to evaluate latency, throughput, and system behavior.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Emulation Platform Integration</span></strong><span style="color:#222222">: Deploy and configure completed SystemC memory models onto the Cadence Palladium emulation platform.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Co-Simulation &amp; Validation</span></strong><span style="color:#222222">: Ensure seamless interface and operational stability between the emulation environment and the memory models.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Performance Evaluation &amp; AI Benchmarking</span></strong><span style="color:#222222">: Execute AI application benchmarks on the Palladium platform.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Value Demonstration</span></strong><span style="color:#222222">: Deliver a detailed performance evaluation report contrasting the VIM system memory architecture against an ideal SRAM baseline across key metrics (latency, bandwidth, energy efficiency, and area) to prove the benefits of VIM.</span></p></li></ul><p style="text-align:justify;min-height: 1.7em;"></p><p style="text-align:justify;"><strong><span style="color:#222222">About the team:&nbsp;</span></strong></p><p style="text-align:justify;"><span style="color:#222222">This role is part of the Product &amp; system team, partnering closely with our cross-functional engineering teams in Product &amp; system&nbsp; and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.</span></p><p><span style="color:#000000"><br></span></p> <br> <p style="min-height: 1.7em;"></p><p><strong><span style="color:#222222">About who you are:</span></strong></p><p><strong><span style="color:#222222">Technical Expertise:</span></strong></p><ul><li><p><strong><span style="color:#222222">Education</span></strong><span style="color:#222222">: BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.</span></p></li><li><p><strong><span style="color:#222222">Software Skills</span></strong><span style="color:#222222">: Exceptional programming skills in systemC, TLM, C/C++ and Python for architectural modeling and scripting.</span></p></li><li><p><strong><span style="color:#222222">Architecture Knowledge</span></strong><span style="color:#222222">: Deep understanding of computer architecture, specifically memory hierarchies (caches, SRAM, DRAM, HBM, memory controllers, and interconnects).</span></p></li><li><p><strong><span style="color:#222222">Modeling Experience</span></strong><span style="color:#222222">: Proven track record of developing and validating system-level performance models using SystemC, Qemu, gem5, or similar architectural simulators.</span></p></li><li><p><strong><span style="color:#222222">Emulation Familiarity</span></strong><span style="color:#222222">: Hands-on experience with hardware emulation platforms (e.g., Cadence Palladium, ZeBu, or Veloce) is a strong plus.</span></p></li></ul><p><strong><span style="color:#000000">Professional skills : </span></strong></p><ul><li><p><span style="color:#000000">Strong analytical skills for measuring, interpreting, and presenting architectural performance trade-offs.</span></p></li><li><p><span style="color:#000000">Ability to author clean, comprehensive technical reports for cross-functional hardware and software teams.</span></p></li><li><p><span style="color:#000000">Autonomy and problem-solving mindset in a high-tech R&amp;D environment.</span><br></p></li></ul><p><strong><span style="color:#222222">Why Join Us:</span></strong></p><ul><li><p style="text-align:justify;"><span style="color:#000000">You will get the opportunity to work at the forefront of memory technology innovation.</span></p></li><li><p style="text-align:justify;"><span style="color:#000000">Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.</span></p></li><li><p style="text-align:justify;"><span style="color:#000000">You can be part of a talented and dedicated team in a fast-paced startup environment.</span></p></li><li><p style="text-align:justify;"><span style="color:#000000">In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.</span></p></li><li><p style="text-align:justify;"><span style="color:#000000">You can count on a motivating total rewards package.</span></p></li><li><p style="text-align:justify;"><span style="color:#000000">Flexible ways of working.</span></p></li></ul><p style="min-height: 1.7em;"></p><p><strong><span style="color:#000000">Join us in shaping the future of compute &amp; memory technology — and celebrating success!</span></strong></p><p style="min-height: 1.7em;"></p><p>Find <a href="https://www.arbeitnow.fr">Jobs in France</a> on Arbeitnow</a>