Senior Formal Verification Engineer - Vector Unit

<p><span style="color: #121317">At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams. </span></p><p><span style="color: #121317">Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.<br /><br /></span><strong><span style="color: #121317">Key Responsibilities</span></strong><span style="color: #121317"><br /><br /></span><strong><span style="color: #121317">Block-Level Execution &amp; Convergence Engineering (90%)</span></strong></p><ul><li><p><strong><span style="color: #121317">End-to-End Testbench Ownership: </span></strong><span style="color: #121317">Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).</span></p></li><li><p><strong><span style="color: #121317">Datapath &amp; Arithmetic Verification:</span></strong><span style="color: #121317"> Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.</span></p></li><li><p><strong><span style="color: #121317">Proof Convergence Management:</span></strong><span style="color: #121317"> Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).</span></p></li><li><p><strong><span style="color: #121317">RISC-V Vector Compliance:</span></strong><span style="color: #121317"> Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.</span></p></li><li><p><strong><span style="color: #121317">Simulation Partnership:</span></strong><span style="color: #121317"> Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.</span></p></li></ul><p><strong><span style="color: #121317">Embedded Mentorship &amp; Best Practices (10%)</span></strong></p><ul><li><p><strong><span style="color: #121317">Formal-Friendly Design:</span></strong><span style="color: #121317"> Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.</span></p></li><li><p><strong><span style="color: #121317">SVA Propagation: </span></strong><span style="color: #121317">Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.</span></p></li></ul><p><br /></p><p style=";"></p><br /><br /><p><strong><span style="color: #121317">Must Have</span></strong></p><ul><li><p><strong><span style="color: #121317">Education:</span></strong><span style="color: #121317"> B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.</span></p></li><li><p><strong><span style="color: #121317">Experience: </span></strong><span style="color: #121317">5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.</span></p></li><li><p><strong><span style="color: #121317">Collaboration Style:</span></strong><span style="color: #121317"> A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.</span></p></li><li><p><strong><span style="color: #121317">Datapath Validation Focus: </span></strong><span style="color: #121317">Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.</span></p></li><li><p><strong><span style="color: #121317">Vector Microarchitecture: </span></strong><span style="color: #121317">Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.</span></p></li><li><p><strong><span style="color: #121317">Formal Tools:</span></strong><span style="color: #121317"> Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.</span></p></li><li><p><strong><span style="color: #121317">Languages:</span></strong><span style="color: #121317"> Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.</span></p></li></ul><p><strong><span style="color: #121317">Nice to Have</span></strong></p><ul><li><p><span style="color: #121317">RISC-V Core Verification.</span></p></li><li><p><strong><span style="color: #121317">RISC-V Ecosystem: </span></strong><span style="color: #121317">Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.</span></p></li><li><p><span style="color: #121317">Emulation platforms (Veloce, ZeBu).</span></p></li><li><p><span style="color: #121317">Core/Bus interface protocols (e.g., AXI/CHI).</span></p></li></ul><p><strong><span style="color: #121317">Essential Soft Skills</span></strong></p><ul><li><p><span style="color: #121317">An </span><strong><span style="color: #121317">adversarial, gap-seeking mindset</span></strong><span style="color: #121317"> — instinctively asks "who actually checks this?" — with a strong umbrella view of the whole core.</span></p></li><li><p><span style="color: #121317">Clear communication across DV, design, and software teams; writes verification plans others can follow.</span></p></li></ul><p style=";"></p><p>Find more <a href="https://www.arbeitnow.com/english-speaking-jobs">English Speaking Jobs in Germany</a> on Arbeitnow</a>